The present invention relates to digital microprocessors, and more particularly to monitoring the operation and performance of digital microprocessors.
Microprocessors are general purpose processors which require high instruction throughputs in order to execute software running thereon, and can have a wide range of processing requirements depending on the particular software applications involved. Microprocessors are now combined with memory circuits and other peripheral circuits into a single integrated circuit and may be custom designed for a particular target system. Often, access to a microprocessor in a target system for software development and debugging is difficult.
Known microprocessor debugging environments provide a means for gaining access to a microprocessor in a target system, of which In Circuit Emulation (ICE) is a commonly favored technique. Typically, a processor in the target system is temporarily replaced by an emulation module that provides connectivity to a test system for monitoring and modifying target system software that is executed by the emulation module.
Alternatively, the target processor is connected to the test system via a test access port, such a JTAG, and the target processor executes the target system software while exchanging test information with the test system via the test access port. JTAG is defined in IEEE 1149.1-1990 xe2x80x9cStandard Test Access Port and Boundary Scan Architecture. Terms and concepts relating to IEEE 1149.1 which are used herein, are explained fully in this IEEE standard. The IEEE 1149.1 standard provides a communication protocol that allows the selection of one or more devices imbedded within a system. This protocol implements the primitives necessary to control on-chip debug and test facilities.
Many different types of processors are known, of which microprocessors are but one example. For example, Digital Signal Processors (DSPs) are widely used, in particular for specific applications, such as mobile processing applications. DSPs are typically configured to optimize the performance of the applications concerned and to achieve this they employ more specialized execution units and instruction sets. Particularly in, but not exclusively, applications such as disk controllers for portable computers and mobile telecommunications, it is desirable to provide ever increasing DSP performance while keeping power consumption as low as possible.
A method and apparatus has now been discovered for emulating a block of memory in a target system with two or more blocks of memory that operate in lock step. Particular and preferred aspects of the invention are set out in the accompanying independent and dependent claims.
In accordance with a first aspect of the invention, there is provided a digital system that has a memory block. The memory block has an address bus for receiving an address, the address decoding circuitry is connected to the address bus. The address decoding circuitry is operable to detect if a received address is within a preselected address block. Bank decode circuitry is connected to the address bus and is operable to detect if a received address is within a preselected address bank. Memory circuitry is connected to the address bus and is operable to transfer data on a data bus in response to a received address if the received address is within the preselected bank and the preselected address block. Control circuitry is connected to the address decoding circuitry. The address decoding circuitry is operable to selectively mask a relative most significant address (msb) bit of the received address corresponding to a size of the memory block in response to the control circuitry. Thus, a plurality of linked memory blocks are operable to selectively detect an address being in the same preselected address block but only one of the plurality of memory blocks is operable to transfer data in response to the bank decode circuitry.
In accordance with another aspect of the present invention, a method for emulating a block of memory in a target system is provided. A first replacement memory block having a first capacity is configured to emulate a first block of target memory in a first target system, wherein the first target memory has a capacity less than or equal to the first capacity. For a second target system, the first replacement memory block is reconfigured to link to a second replacement memory block to emulate a second block of target memory by masking a relative most significant bit (msb) of a memory request address received by the first replacement memory block and by the second replacement memory block. The linked first replacement memory and second replacement memory have a combined second capacity, wherein the second target memory has a capacity larger than the first capacity but less than or equal to the combined second capacity.